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512kx8-Bit Dynamic RAM
HYB 514800BJ -60/-70/-80
Advanced Information
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512 288 words by 8-bit organization 0 to 70 C operating temperature Fast access and cycle time RAS access time: 60 ns (-60 version) 70 ns (-70 version) 80 ns (-80 version) CAS access time: 20 ns Cycle time: 110 ns (-60 version) 130 ns (-70 version) 150 ns (-80 version) Fast page mode cycle time 45 ns (-60 version) 45 ns (-70 version) 50 ns (-80 version) Single + 5 V ( 10 %) supply with a built-in Vbb generator
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Low power dissipation max. 605 mW active (-60 version) max. 550 mW active (-70 version) max. 468 mW active (-80 version) Standby power dissipation: 11 mW standby standby (TTL) 5.5 mW max.standby (CMOS) Output unlatched at cycle end allows twodimensional chip selection Read, write, read-modify write, CAS-beforeRAS refresh, RAS-only refresh, hidden refresh, fast page mode capability All inputs and outputs TTL-compatible 1024 refresh cycles / 16 ms Plastic Packages: P-SOJ-28-2 400 mil width
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Ordering Information Type HYB 514800BJ-60 HYB 514800BJ-70 HYB 514800BJ-80 Ordering Code Q67100-Q849 Q67100-Q850 Q67100-Q851 Package P-SOJ-28-2 P-SOJ-28-2 P-SOJ-28-2 Descriptions DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 80 ns)
Semiconductor Group
125
01.95
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
The HYB 514800BJ is the new generation dynamic RAM organized as 512 288 words by 8-bit. The HYB 514800BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514800BJ to be packed in a standard plastic 400mil wide P-SOPJ-28 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented feature include single + 5 V ( 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Pin Definitions and Functions A0-A8,A9R RAS CAS WRITE OE IO1 - IO8 N.C. Address Input Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output No Connection Power Supply (+ 5 V) Ground (0 V)
VCC VSS
Pin Configuration (top view)
P-SOJ-28-2 ( 400 mil width)
Semiconductor Group
126
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
Block Diagram
Semiconductor Group
127
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
Absolute Maximum Ratings Operating temperature range ............................................................................................0 to 70 C Storage temperature range......................................................................................- 55 to + 150 C Soldering temperature ............................................................................................................260 C Soldering time .............................................................................................................................10 s Input/output voltage ........................................................................................................ - 1 to + 7 V Power Supply voltage ..................................................................................................... - 1 to + 7 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %, tT = 5 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current, any input (0 V < Vin < 7, all other input = 0 V) Output leakage current (DO is disabled, 0 < VOUT < VCC) Average VCC supply current -60 version -70 version -80 version Standby VCC supply current (RAS = CAS = Vih) Average VCC supply current during RAS-only refresh cycles -60 version -70 version -80 version Average VCC supply current during fast page mode operation -60 version -70 version -80 version Symbol Limit Values min. max. 6.5 0.8 - 0.4 10 10 2.4 - 1.0 2.4 - - 10 - 10 Unit Test Condition V V V V A A mA - - - 110 100 90 2 mA mA - - - 110 100 90 mA - - - 70 60 50
2) 3) 1) 1) 1) 1) 1)
Vih Vil Voh Vol II(L) Io(L) ICC1
1)
2) 3)
ICC2 ICC3
-
-
2)
ICC4
Semiconductor Group
128
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %, tT = 5 ns Parameter Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current during CAS before RAS refresh mode -60 version -70 version -80 version Symbol Limit Values min. max. 1 - Unit Test Condition mA mA - - - 110 100 90
1)
ICC5 ICC6
2)
Semiconductor Group
129
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
AC Characteristics 4) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -60 min. Random read or write tRC time Read-write cycle time tRWC Fast page mode cycle time Fast page mode read/write cycle time Access time from RAS 6) 11) Access time from CAS 6) 11) 110 165 45 100 - - - - 0 0 3 40 60 60 20 20 60 40 max. - - - - 60 20 30 40 - 20 50 - 10000 200000 10000 - - - min. 130 185 45 100 - - - - 0 0 3 50 70 70 20 20 70 45 Limit Values -70 max. - - - - 70 20 35 40 - 20 50 - 10000 200000 10000 - - - min. 150 205 50 105 - - - - 0 0 3 60 80 80 20 20 80 50 -80 max. - - - - 80 20 40 45 - 20 50 - 10000 200000 10000 - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tPC tPRWC tRAC tCAC
tAA Access time from 6) 12) column address
Access time from CAS precharge 6) CAS to output in low-Z 6) Output buffer turn-off delay from CAS 7) Transition time (rise and fall) 5) RAS precharge time RAS pulse width RAS pulse width in fast page mode CAS pulse width RAS hold time CAS hold time RAS hold time from CAS precharge
(Fast page mode)
tCPA tCLZ tOFF tT tRP tRAS tRASP tCAS tRSH tCSH tRHCP
CAS precharge to WRITE delay time
(FPM read-modify-write)
tCPWD
60
-
65
-
70
-
ns
Semiconductor Group
130
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
AC Characteristics (cont'd)4) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -60 min. RAS to CAS delay time 11) RAS to column address delay time 12) CAS to RAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time max. 40 30 min. 20 15 Limit Values -70 max. 50 35 min. 20 15 -80 max. 60 40 ns ns Unit
tRCD tRAD
20 15
tCRP tCP tASR tRAH tASC
5 10 0 10 0 15 30 0 0 0 10 50 10 20 20 0
- - - - - - - - - - - - - - - - 131
5 10 0 10 0 15 35 0 0 0 15 55 15 20 20 0
- - - - - - - - - - - - - - - -
10 10 0 10 0 15 40 0 0 0 15 60 15 20 20 0
- - - - - - - - - - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Column address hold tCAH time Column address to RAS lead time Read command setup time Read command hold time 8) Read command hold time ref. to RAS 8) Write command hold time Write command hold time ref. to RAS Write command pulse width Write command to RAS lead time Write command to CAS lead time Data setup time 9) Semiconductor Group
tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
AC Characteristics (cont'd)4) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -60 min. Data hold time Refresh period Write command setup time 10)
9)
Limit Values -70 min. 15 - 0 50 100 65 5 15 0 40 max. - 16 - - - - - - - - min. 15 - 0 50 110 70 5 15 0 40 -80 max. - 16 - - - - - - - - max. - 16 - - - - - - - -
Unit
tDH tREF tWCS
15 - 0 50 90 60 5 15 0 30
ns ms ns ns ns ns ns ns ns ns
CAS to WRITE delay tCWD time 10) RAS to WRITE delay tRWD time 10) Column address to tAWD WRITE delay time 10) CAS setup time (CBR tCSR cycle) CAS hold time (CBR cycle) RAS to CAS precharge time CAS precharge time (CAS before RAS counter test cycle) Write to RAS precharge time (CBR cycle) Write to RAS hold time (CBR cycle) OE command hold time OE acces time RAS hold time referenced to OE Output buffer turn-off delay from OE Data to CAS low delay 14)
tCHR tRPC tCPT
tWRP
10
-
10
-
10
-
ns
tWRH tOEH tOEA tROH tOEZ tDZC
10 20 - 10 0 0
- - 20 - 20 -
10 20 - 10 0 0
- - 20 - 20 -
10 20 - 10 0 0
- - 20 - 20 -
ns ns ns ns ns ns
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132
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
AC Characteristics (cont'd)4) TA = 0 to 70 C; VCC = 5 V 10 %; tT = 5 ns Parameter Symbol -60 min. Data to OE low delay 14) CAS high to data delay 15) OE high to data delay 15) CAS hold time after OE low max. - - - - min. 0 20 20 20 Limit Values -70 max. - - - - min. 0 20 20 20 -80 max. - - - - ns ns ns ns Unit
tDZ0 tCDD tODD tOECH
0 20 20 20
Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A9) Input capacitance (RAS, CAS, WE) Output capacitance (IO1 to IO8) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
Ci1 Ci2 Cio
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HYB 514800BJ -60/-70/-80 512k x 8 DRAM
Notes:
1) All voltages are referenced to VSS 2) 3)
ICC1 , ICC3 , ICC4 and ICC6 depend on cycle rate. ICC1 , ICC4 depend on output loading.
4) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5)
Vih (min.) and Vil (max.) are reference levels for measuring timing of input signals. Transition times are also measured between Vih and Vil . toff (max.), tOEZ (max.) defines the time at which the output achieves the open-circuit conditions and are not
referenced to output voltage levels.
6) Measured with a load equivalent to 2 TTL loads and 100 pF. 7)
8) Either tRCH or
tRRH must be satisfied for a read cycle.
9) These parameters are references to the CAS leading edge in early write and to the WRITE leading edge in read-write cycles. 10) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a readwrite cycle and I/O will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 11) Operation within the tRCD (max.) limit ensure that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRAD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC . 12) Operation within the tRAD (max.) limit ensured that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA . 13) AC measurements assume tT = 5 ns. 14) Either tDZC or tDZO must be satisfied. 15) Either tCDD or tODD must be satisfied.
Semiconductor Group
134
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
A0 - A9
V IH VIL
Row Address
tRCH tRAH tRCS tRRH tAA tOEA
WRITE
V IH VIL
OE
V IH VIL
tDZC tDZO tCAC tCLZ
Hi Z
tCDD tODD
I/O1-I/O8 (Inputs)
V IH VIL
tOFF tOEZ
Valid Data Out Hi Z
I/O1-I/O8 (Outputs) V
V OH OL
tRAC
"H" or "L"
Read Cycle
Semiconductor Group
135
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
A0 - A9
V IH VIL
.
Row Address
tRAH
WRITE
V IH VIL
tWCS
tCWL t WP tWCH tRWL
OE
V IH VIL
tDS
I/O1-I/O8 (Inputs)
V IH VIL
tDH
Valid Data In
OH I/O1-I/O8 (Outputs) V OL
V
Hi Z
"H" or "L"
Write Cycle (Early Write)
Semiconductor Group
136
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
V IH
CAS
VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
A0 - A9
V IH VIL
.
Row Address
tRAH
WRITE
V IH VIL
tCWL tRWL tWP
tOEH
OE
V IH VIL
tODD tDZO tDZC tDS tOEZ
tDH
I/O1-I/O8 (Inputs)
V IH VIL Valid Data
tCLZ tOEA
Hi-Z
I/O1-I/O8 VOH (Outputs)
V OL
Hi-Z
"H" or "L"
Write Cycle (OE Controlled Write)
Semiconductor Group
137
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRWC tRAS
V IH VIL V IH
tRP
RAS
tCSH tRCD tRSH tCAS tCRP
CAS
VIL
tRAH
A0 - A9
V IH VIL
tCAH tASC
Column Address
tASR
Row Address
tASR
Row Address
tRAD
V IH
tAWD tCWD tRWD
tCWL tRWL tWP
WRITE
VIL
tAA tRCS
V IH
tOEA
tOEH
OE
VIL
tDZO tDZC
tDS tDH
Valid Data in
I/O1-I/O8 (Inputs)
V IH VIL
tCLZ tCAC
Data Out
tODD tOEZ
I/O1-I/O8 OH (Outputs) V OL
V
tRAC
"H" or "L"
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
138
tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC
Column Address Column Address
V
RAS
IH
V IL
tCSH tRCD tCAS tRAL tASR
Row Address
tRSH tCRP
Semiconductor Group
V
CAS
IH
V IL
tASR tASC
Column Address
tRAD tRAH tCAH tCAH
V
A0-A9
IH
V IL
Row Address
Fast Page Mode Read-Modify-Write Cycle
V
tRCS tAA tOEA tOEA tCPA tDZC
Data In
tRWD tCWD tCWL tAWD tWP tWP tOEA tAWD tCWL tAWD
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
WRITE
IH
V IL
139
tWP
V
OE
IH
V IL
tCPA tODD
Data In
V
IH
tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ tDH tDS
Data Out Data Out
tDZC tCLZ tOEH
tODD
Data In
I/O1-I/O8 (Inputs) V IL
tODD tAA
tOEH tCAC tOEZ tDS tDH
tOEH tAA tOEZ tDS
Data Out
tDH
I/O1-I/O8 VOH (Outputs) V
OL
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
"H" or "L"
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRASP
V IH
tRP
RAS
VIL
tRCD
V IH
tPC tCP tCAS tCSH tCAS
tRHCP tRSH tCAS tCRP
CAS
VIL
tRAH tASR
A0-A9
V IH VIL
Row Addr
tASC
tCAH
Column Address
tASC
tCAH tASC
tCAH tASR
Row Address Column Address
Column Address
tRAD tRCH tRCS tRCS tRCS
tRCH
V IH
WRITE
VIL
V IH
tAA tOEA
tCPA tAA tOEA
tCPA tAA tOEA tDZC tDZO tODD
tRRH
OE
VIL
tDZC tDZO tODD tCAC tRAC tCLZ tOFF tOEZ
Valid Data Out
tDZC tDZO
tCDD tODD
I/O1-I/O8 (Inputs)
V IH VIL
tCAC tOFF tCLZ tOEZ
Valid Data Out
tCAC tCLZ
tOFF tOEZ
Valid Data Out
I/O1-I/O8 OH (Outputs) V
OL
V
"H" or "L"
Fast Page Mode Read Cycle
Semiconductor Group
140
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRASP
V IH
tRP
RAS
VIL
tPC tCAS tRCD tCP
tCAS
tRSH tCAS tCRP
V IH
CAS
VIL
tRAL tRAH tASR tCAH tASC
Column Address
tASC tCAH
Column Address
A0-A9
V IH VIL
tASC
tCAH
tASR
Column Address
Row Addr
Column Address
tRAD
V IH VIL
tCWL tWCS tWCH tWP
tCWL tWCS tWCH tWP
tCWL tRWL tWCS tWCH tWP
WRITE
OE
V IH VIL
tDH tDS
I/O1-I/O8 (Inputs)
V IH VIL Valid Data In
tDH tDS
Valid Data In
tDH tDS
Valid Data In
OH I/O1-I/O8 (Outputs) V OL
V
HI-Z
"H" or "L"
Fast Page Mode Early Write Cycle
Semiconductor Group
141
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCRP tRPC
V IH
CAS
VIL
tRAH tASR
tASR
Row Address
A0-A9
V IH VIL
Row Address
OH I/O1-I/O8 (Outputs) V OL
V
HI-Z
"H" or "L"
RAS-Only Refresh Cycle
Semiconductor Group
142
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRC tRP
RAS
V IH VIL
tRAS
tRP
tRPC tCSR
CAS
V IH VIL
tCRP tCHR tRPC
tCP tWRP tWRH
WRITE
V IH VIL
tOEZ
OE
V IH VIL
tCDD
I/O1-I/O8 (Inputs)
V IH VIL
tODD
OH I/O1-I/O8 (Outputs) V OL V HI-Z
tOFF
"H" or "L"
CAS-Before-RAS Refresh Cycle
Semiconductor Group
143
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRC
V IH VIL
tRC tRP tRAS tRP
tRAS
RAS
tRCD
V IH VIL
tRSH tCHR tCRP
CAS
tRAD tRAH tASR tASC tWRP tCAH tWRH tASR
Row Address
A0-A9
V IH VIL
Row Addr
Column Address
tRCS
WRITE
V IH VIL
tRRH
tAA tOEA
OE
V IH VIL
tDZC tDZO
tCDD tODD
I/O1-I/O8 (Inputs)
V IH VIL
tCAC tCLZ tRAC tOEZ
Valid Data Out
tOFF
I/O1-I/O8 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Read)
Semiconductor Group
144
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
tRC tRP
RAS
V IH VIL
tRC tRAS tRP
tRAS
tRCD
V IH VIL
tRSH
tCHR
tCRP
CAS
tRAD tRAH tASR tASC tCAH
Column Address
tASR
Row Address
A0-A9
V IH VIL
Row Addr
tWCS
tWCH tWP
WRITE
V IH VIL
OE
V IH VIL
tDS
I/O1-I/O8 (Inputs)
V IH VIL
tDH
Valid Data
OH I/O1-I/O8 (Outputs) V OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Early Write)
Semiconductor Group
145
HYB 514800BJ -60/-70/-80 512k x 8 DRAM
V
tRAS
IH
tRP tRSH tCAS
RAS
V
IL
tCSR
V
tCHR
tCPT
CAS
IH
V
IL
V
tASC
IH
tCAH tAA tCAC
tRAL
tASR
Row Address
A0-A9
V
IL
Column Address
Read Cycle
WRITE
V V IH
tWRP tWRH
IL
tRCS
tRRH tRCH
tOEA
OE
V V IH IL
I/O1-I/O8 (Inputs)
V V
tDZC tDZO tCLZ
tODD tOEZ
Valid Data Out
tCDD tOFF
IH
IL
I/O1-I/O8 (Outputs)
V OH VOL
Write Cycle
V IH
tWRP tWRH
tWCS
tRWL tCWL tWCH
WRITE
V V
IL IH
OE
V
IL
tDS
I/O1-I/O8 (Inputs) I/O1-I/O8 (Outputs)
V V IH IL HI-Z
tDH tCWL tRWL tWP tOEH tDS tDH
Data In
Valid Data In
V IH V IL V IH
Read-Modify-Write Cycle
WRITE
V IL
tWRP
tWRH
tRCS tAA
tAWD tCWD tCAC tOEA
V
OE
IH
V
IL
I/O1-I/O8 (Inputs) I/O1-I/O8 (Outputs)
V V
IH
tDZC tDZO tCLZ
HI-Z
IL
tCAC
D.Out
V OH VOL
tODD tOEZ
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
146

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